Design of Programmable Memory BIST for Embedded Dual Ports SRAM;
嵌入式双端口SRAM可编程内建自测试结构的设计
Embedded Flash Memory BIST For System-on-a-Chip;
SoC嵌入式flash存储器的内建自测试设计
An All-Digital BIST Scheme for the ADC Test;
全数字的模数转换器内建自测试方案
Implementation of quadratic orthogonal demodulation and built-in self test
二次正交解调算法及内建自测试的实现
Aiming at the mixed-signal circuit testing,an integrated built-in self test(BIST) architecture for testing on-chip high speed ADC was presented.
针对混合信号电路的测试问题,提出了一种内建自测试(BIST)结构,分析并给出了如何利用该结构来计算片上高速模数转换器(ADC)的静态参数。
The built-in self test(BIST)method for IP core and the design method for test-oriented IP core are introduced.
介绍了用于IP核测试的内建自测试方法(BIST)和面向测试的IP核设计方法,指出基于IP核的系统芯片(SOC)的测试、验证以及相关性测试具有较大难度,传统的测试和验证方法均难以满足。
The principle of the SRAM build-in self-test achieving and some advanced algorithms of march are analyzed in details and a typical design method of SRAM BIST is introduced by designing BIST circuits of 16k×32bit SRAM and is implemented on the Altera-EP1S25.
文中介绍了SRAM的典型故障类型和几种常用的测试方法,同时详细分析了嵌入式SRAM存储器内建自测试的实现原理以及几种改进的March算法,另外,以16k×32bitSRAM为例,给出了SRAM内建自测试的一种典型实现,并在Altera-EP1S25上实现。
As a new method of design for testability build-in self-test can prominently improve the testability of the circuits.
内建自测试作为一种新的可测性设计方法,能显著提高电路的可测性。
The Research on Low Power Built-in Self-test Design;
低功耗内建自测试设计方法研究
Study on Built-In Self-Test Methodology for Fault Diagnosis of Mixed-Signal Circuits;
混合信号电路故障诊断的内建自测试（BIST）方法研究
A low power test approach for test or built-in self-test based on arithmetic additive generator is proposed in this paper.
本文提出了一种基于算术加法生成器的测试或内建自测试的低功耗测试方法。
To reduce the storage volume of the test data during the built-in self-test(BIST),a new BIST technique based on two dimensional compression of test data is presented.
为压缩内建自测试(BIST)期间所需测试数据存储容量,提出了一种新的基于测试数据两维压缩的BIST方案。
This method can be applied in the mixed-signal circuits test and in the Built-In Self-Test(BIST).
利用伪随机序列作为测试激励,通过计算输入输出的互相关函数得到K维特征空间,在特征空间的基础上进行分析,判别电路有无故障,实验证明该方法简单可行,且提高了测试的效率和正确性,适用于模拟及混合信号测试,适用于混合信号电路的内建自测试(BIST)。
The advantagesand means of built-in self-test(BIST) are exhaustively discussed.
分析了数字VLSI电路的传统测试手段及其存在问题,通过对比的方法,讨论了内建自测试(BIST)技术及其优点,简介了多芯片组件(MCM)内建自测试的目标、设计和测试方案。
A Study on Memory Built-in Self-Test and Functional Core Testing;
存储器内建自测试及内核功能测试研究
An All-Digital BIST Scheme for the ADC Test
全数字的模数转换器内建自测试方案
The Design and Realization of the Built-in Self Test in X Microprocessor;
X型CPU内建自测试系统的设计与实现
Mbist Diagnosis Algorithm and Self-Repair;
嵌入式memory内建自测试算法
Design and Realization of SATA Build In Self Test;
SATA内建自测试的电路设计与实现
Research for Built-In Self-Test Based on FPGA
基于FPGA的内建自测试的实现研究
Research on BIST test method for network-on-chip FIFOs
片上网络FIFOs的内建自测试方法研究
Design and Simulation of Memory BIST Based on March C+ Algorithm
基于March C+算法的存储器内建自测试自测试设计与仿真
Design of Template Based on Built-in Self Test and Bench Mark Program
基于软件内建自测试的模板和基准程序设计
The Study on Built-in Self-test (BIST) for Integrated Circuits Based-on Multiple Scan Chains;
基于多扫描链的集成电路内建自测试方法研究
Boundary-Scan Based Built-in-Self-Test Technology and Its Application;
基于边界扫描的内建自测试技术及其应用
Design of the Floating Point Adder and Research of Its Bist
FPU中浮点加法器的设计及其内建自测试的研究
The Study on Built-in Self-Test Method Based on Multi-Scan Chains
基于多扫描电路的内建自测试方法研究
Implementation of quadratic orthogonal demodulation and built-in self test
二次正交解调算法及内建自测试的实现
Study on Built-In Self-Test Methodology for Fault Diagnosis of Mixed-Signal Circuits;
混合信号电路故障诊断的内建自测试（BIST）方法研究
Research on Accumulator-Based Built-In Self-Test for DSP Data Path;
基于累加器的DSP数据通路的内建自测试技术的研究
Testing and Evaluation on Thermal Environment of Hallway in Civil Building with Natural Ventilation
民用建筑内走廊自然通风热环境测试及评价
Modeling for Spacecraft Automated Test and Design of Automated Test Language
航天器自动化测试建模及自动化测试语言设计
