We present a staggered buffer connection method that provides flexibility for buffer insertion while designing global signal networks using the tile-based FPGA design methodology.
针对使用拼接单元块设计方法的岛式FPGA,介绍了一种交叉连接的方法,可以为其全局信号网络的缓冲器插入提供可变性。
The paper discusses the clock operation solution by phase locked loops(PLLs)and global clock network offered by the programmable logic device based on the SRAM technology.
讨论了基于SRAM技术的可编程逻辑器件提供的PLL和全局时钟网络对时钟操作的解决方案。
