The results of computer simulation show that this method does not require the sampling interval to satisfy the Nyquist sampling criteria and only needs few sampling points to attain very high testing precision,so we can improve the testing speed and effectively reduce the truncation error caused by finite scanning plane on the premise of ensuring t.
计算机模拟结果表明 ,这种方法不要求取样间隔一定要满足奈奎斯特取样准则 ,只需较少的取样点数即可达到很高的测试精度 ,从而能够在保证测试精度的前提下 ,提高测试速度并有效减小由于有限扫描面所引起的截断误差 。
The malfunction of UST-4 evenness tester was reduced by optimizing the temperature, the humidity, testing speed and other measures.
介绍了UST-4型条干均匀度仪工作原理,通过优化温湿度、测试速度等措施,降低了该仪器分析样品的故障率,同时对常见仪器故障的影响因素进行了分析,确保该仪器稳定运行。
In this paper we report the best testing way by 8098 in which the 1HZ～10MHZ stable signal frequency or period is tested within 1/1000 test precision, the design,the design of hardware and software, error analysis, test range are discussed,how to choose the best pulse number counted automaticlly is also given in order to raise test speed or precision.
对频率为 1Hz～ 10MHz的稳定信号 ,在保证 1 10 0 0的测试精度下 ,用 80 98单片机完成其频率或周期的最优测试方法 ,讨论其测试的硬软件设计、误差分析、测试范围分析以及为提高测试速度或测试精密度时N的最优值确
The research of multi - fault test generation for combinational logic circuits;
组合逻辑电路多故障测试生成算法的研究
Binary decision diagram method for test generation of digital circuits;
数字电路测试生成的二元判定图方法
Neural networks based test generation algorithm for combinational logic circuits;
基于神经网络的组合电路测试生成算法
A path delay fault testing generation algorithm for digital circuits based on neural network is proposed because the testing generation for path delay fault in digital circuits is more difficult.
针对数字电路路径时滞故障测试生成较难的问题,提出了基于神经网络的数字电路路径时滞故障测试生成算法。
A path delay fault testing generation algorithm based on Boolean difference for digital circuits is proposed because the testing generation for path delay fault in digital circuits is more difficult.
针对数字电路路径时滞故障测试生成较难的问题提出了一种基于布尔差分的数字电路路径时滞故障测试生成算法。
In order to obtain better failure coverage and testing set of digital circuit and reduce the reverse backtracking,many bionics algorithms are applied to testing generation of circuit.
数字集成电路的快速发展对电路测试提出了日益紧迫的要求,为获得较好的数字电路的故障覆盖率和测试集,减少反向回溯,很多仿生学算法应用到了电路的测试生成当中,现介绍了在测试生成领域中有重大影响的几种仿生优化算法以及各自特点。
speed test cassette
速度测试卡型盒式磁带
testing method for flammability of clothes burning rate method
织物燃烧试验法：燃烧速度测试法
A Sort of Easy Program to Test the Input Speed of Chinese or English Words
一则简易的中英文输入速度测试程序
Development of human reaction speed test system using MAX Ⅱ CPLD
用MAX Ⅱ CPLD开发人体反应速度测试系统
Study on Present Situation of the Domestic Burning Velocity
国内火焰燃烧速度测试研究现状浅析
Application of Single Chip Microcomputer in Acceleration test of Assistant Flying Jamming
单片微机在助飞干扰器加速度测试中的应用
The Speed Measure and Control of Handler Test Machine
IC芯片测试设备机械抓手的速度测控
Calculation and measurement of speed of diametric fragments of metal-back blasting caps
金属壳雷管径向破片速度计算及测试
Structure Design and Accuracy Test of the Large Ratio Friction Transmission Apparatus;
大速比摩擦传动结构设计和精度测试
Decarburizing Speed Analysis for 180 t Converter in Angang
180t转炉脱碳速度的测试与分析
Effects of Scan Rate of the Fourier Transformation Spectroscopy on Test Result
傅里叶光谱仪扫描速度对测试的影响
Research and Manufacture on High Precision Dynarmic Integrated Test Platform of Retarders
高精度减速顶动态综合测试台的研制
Missile-borne Storage Measurement and Test Instrument of Acceleration Based on CPLD
基于CPLD的弹载加速度存储测试仪
Parallel stream scheduling for high-speed performance test systems
高速性能测试系统的并行流调度机制
A Preliminary Study of the Validity of the Cet-4 Fast Reading Test
大学英语四级考试快速阅读测试效度初探
Testing and analysis of dynamometer velocity ability for rowing athletes;
赛艇运动员测功仪速度素质的测试分析
The meter has the characteristics of having high speed, high accuracy, easy operation and direct display.
具有测试速度快、度高、用方便、示直观等优点。
Speed measurement for runway friction measurements based on GPS/hall sensor fusion
基于GPS/霍尔转速传感器融合的机场跑道摩擦系数测试车速度测量
