Compared with the synchronized counter,the asynchronous counter faced two prominent difficult questions in design: One is the selection of clock signals of various triggers,the other is the correct gain of the karnaugh map at the time when the is simplified into the equation of state for varions triggers.
和同步计数器相比,异步计数器的设计面临2个突出的难点:一个是各触发器时钟信号的选取,一个是从状态转换图化简整理各触发器的状态方程时卡诺图的正确获取。
On the base of the traditional approaches for designing synchronous sequential circuits,a new approach for designing asynchronous sequential logic circuit is proposed in this paper where the trigger pulses can be directly obtained from sequential waveforms in sequential circuits,and the next state Karnaugh maps can be acomplished according to the state transformations caused by clock signals.
该方法直接从时序电路的时序波形图,获得触发器的触发脉冲;根据时钟信号作用下引起的状态转换,填写次态卡诺图。
This paper introduces IBIS model and its applications in the design of computer high-speed system, and gives the waveform of clock signal simulation in detail.
介绍了IBIS模型及其模型高速线路设计中的应用研究,给出了时钟信号仿真的波形,仿真结果证明了在微机高速线路设计中引入IBIS模型的重要性和必要性。
With the development in computer,semiconductor and communication technology,the signal clock in a circuit system works faster and the signal rise time gets shorter.
随着计算机、半导体和通信技术的发展,电路系统的信号时钟速度越来越快,信号上升时间也越来越短,导致因底层模拟信号完整性问题引发的数字错误日益突出。
The extinction ratio of optical clock signal can be greatly increased after passing through birefringent fiber loop mirror(FLM, due to its flexibly tunable filtering characteristics,and then the clock signal quality is improved.
时钟信号的好坏在同步、解复用和光判决中起着决定性的作用,双折射光纤环镜具有灵活可调的滤波特性,光时钟信号通过双折射环形镜可以使其消光比得到改善,从而提高时钟信号的质量。
Base on the comparison of each kind of structure of toggle flip-flop(TFF),using a high-speed frequency divider circuit structure,which controlled by single clock signal to achieve,the design and realization of a 1∶8 frequency divider for optical fiber communication is introduced.
在比较反转触发器(TFF)的各种结构基础上,采用一种单时钟信号控制,实现高速分频的电路结构,设计实现了用于光通信中时钟数据恢复电路的八分频器。
Based on the principles of confirmation TB signal generation, clock TB signal, feedback confirmation TB signal, and actual confirmation TB signal were monitored by multiple-trace storage oscilloscope for BOOMBOX digital blaster and SSS300 analog blaster, and quantitative analysis of the factors that affect the accuracy of the confirmation TB signal was carried out.
基于BOOMBOX数字爆炸机和SSS300模拟爆炸机的原理分析,采用多踪存储示波器对两种爆炸机的钟时断信号、回复验证时断信号和实际验证时断信号进行了监控测试,对验证时断信号准确性影响因素进行了量化分析,研究结果为提高验证时断信号的准确性、正确判断与评价地震记录的质量提供了依据。
Circuit reliability and clock signal integrity are very important constraints in VLSI (very large scale integration) circuit designs.
为诊断大规模集成电路设计过程中电迁移可靠性及分析时钟信号完整性,开发一种用于集成电路片上时钟信号模拟软件Etsim3。
A clock signal with 1 million pulses per second is referred to as a 1 megahertz.
每秒钟有一百万个脉冲及时钟信号，也称兆赫.
Supports external wait signal to expend the buS cycle.
支持外部等待时钟信号延长总线周期。
The Research on Transmission of Clock Signals in Digital Synchronization Network;
数字同步网时钟信号传递问题的研究
Represents a crystal clock signal generator. Number of electrodes can be specified.
表示晶体时钟信号发生器。可指定电极数目。
Simulation and Termination Methods for Board Level High Speed Clock Signals
板级高速时钟信号建模仿真与端接方法
The transition from voltage to no voltage is referred to as the trailing edge of a clock signal.
电感从一定值下降到0值的跃迁叫做时钟信号的后沿。
Generation of Multi-Wavelength Optical Pulses and Electrical Clock Signal Utilizing Optoelectronic Oscillator with Single Light Source
利用单光源光电振荡器实现多波长光脉冲与电时钟信号产生
Traces on opposite sides of the board should run at right angles to each other.
快速切换的信号，例如时钟信号，应该用地线屏蔽，以避免将噪声辐射到其他部分。
The weather forecast is followed by the pips at 6 o'clock.
天气预报之後即为6点钟报时信号.
A New Mixed-mode Design of DCM Clock Delay Locked Loop
一种新型混合信号时钟延时锁定环电路设计
How often should this signal be sent? (minimum 15 minutes)
发送该信号的时间间隔是多少?(最少 15 分钟)
Also, ask the operator to signal you when the three minutes have passed.
还有，叫电话员在3分钟过去时给个信号。
The time base was given both by a crystal clock and the broadcast standard signals.
时间标准是由石英钟和广播标准信号提供的。
Let's set the clock by the radio time signal.
咱们照着收音机的报时信号把钟对一对。
TIME: The scanner will halt on a signal it encounters, and will hold five seconds.
时间：扫描将停在发现的一个信号频率上5秒钟。
Rotate turn signal bulb socket counterclockwise, pull on bulb to remove.
逆时钟旋转转向信号灯灯泡插座，拔下灯泡。
Of course the sampling clock is itself a digital signal.
时钟本身也是数字信号，也会干扰模拟电路。
Research on the Clock Jitter Effects on the Performance of GPS Tracking
采样时钟抖动对GPS信号跟踪性能影响研究
