The development of special geomagnetic DC-1 digital clock;
地磁专用DC-1型数字钟的研制
It can make the design process simple with the application of Multisim8 to design and simulate digital clock.
应用Multisim8进行数字钟设计与仿真。
By showing some program codes and emulational wave charts,the paper introduces the way to design digital electro circuits with VHDL in details and gives us an example of designing a digital clock.
以一款数字钟设计为例,较详细的介绍了如何用VHDL语言设计数字电路,并给出了部分程序、仿真波形图,并在MAX+plusII中进行编译、仿真、下载。
Design of multifunctional digital clock in instrument based on FPGA device;
基于FPGA的仪表用多功能数字时钟的嵌入设计
Design of digital clock based on VHDL;
基于VHDL的数字时钟的设计
A design of digital clock based on FPGA
基于FPGA的数字时钟的设计
Design of Digital Clock Based on Multisim8
基于MULTISIM8的数字钟的设计
These clocks are called digital clocks, and they tell the time with a set of numerals which appear in a little window.
这种钟叫做数字钟，它用一组出现在小显示屏上的数字报时。
Studies on ACEL Display Panel s Driving Circuit Base on Digital Clock;
基于数字钟的ACEL屏驱动电路的研究
Design and Realization of Digital Clock Based on MAX+plusII;
基于MAX+plusII的数字钟的设计与实现
RESEARCH AND TRIAL OPERATION ON THE SEISMIC DIGITAL CLOCK
地震专用数字钟的研制及试运行结果
Research on EDA Designed Experiment Teaching;
EDA设计性实验课教学研究——数字钟的设计
a digital watch [clock]
数字式手表 [时钟]
digital electronic chronometer
数字式电子精密钟表
is a number from 0 to 59 representing the minute
介于0到59之间的数字，代表分钟数
The number of bytes per second from this flow which have been sent
每秒钟从这个流量中发送的字节数
The number of bytes per second from this flow which have been scheduled
每秒钟从这个流量中计划的字节数
The Research on Transmission of Clock Signals in Digital Synchronization Network;
数字同步网时钟信号传递问题的研究
The Design Process and Emulation based on AT89C51 Digital Time Unit
基于AT89C51数字时钟设计过程与仿真
Design of Digital Phase Locked Loop Used in SDH Equipment Clock
SDH设备时钟中的数字锁相环设计
Study on Digital Clock Based on AT89C51 Single-chip Microcomputer
基于AT89C51单片机数字时钟的研究
Digitalization and University Heritage in Modern Time:Professor Zhong Jingwen's Workstation
数字化与现代大学遗产:钟敬文工作站
an unadjusted figure of 8.5 percent; the unadjusted clock is running fast;.
8.5%未调整的数字；这个没有调过的时钟快了些。
Requirements for clock and synchronization equipment used in the digital network
GB12048-1989数字网内时钟和同步设备的进网要求
