DPLL Governing System of Preshrunk Finish Machine;
预缩机的数字锁相环调速系统
A Research of Fast Frequency Hopping Synthesizers based on PLL;
基于锁相环快速跳频源的设计
A PLL-based Digital DC-DC Controller;
基于锁相环的数字化DC-DC控制器
11.6-GHz 0.18-μm monolithic CMOS phase-locked loop;
11.6-GHz 0.18-μm CMOS锁相环电路(英文)
Method for detecting harmonics and reactive currents in single-phase circuit without phase-locked loop;
一种无锁相环的单相电路谐波和无功电流检测方法
A CMOS charge pump for high-performance phase-locked loop;
一种可用于高性能锁相环的CMOS电荷泵
Design of a 2.5V 0.25 μm high-speed CMOS phase locked loop;
一种2.5V 0.25μm高速CMOS锁相环设计
Research on double-integrating A/D converter and phase locked loop frequency doubler;
双积分A/D转换器与锁相环倍频器研究
An improvement on thyristor trigger based on synchronous circuit of phase locked loop;
基于锁相环同步的晶闸管触发器的改进
Cooperative control scheme for phase lock loop and load sharing in parallel operation of UPS with no control interconnections;
UPS无互联线并联中锁相环与负载均分的协调控制方案
A frequency and phase lock loop for carrier recovery;
用作载波恢复的锁频锁相环
It consists of an automatic frequency tracking circuit of phase lock loop and phase shift PWM control circuit.
报道了一种消化道微创诊疗微系统的无线体外供能装置,它主要由利用锁相环的自动频率跟踪电路和采用移相的调功电路构成。
In order to improve the speed stability precision of turntables of nongyroscopic north seeking systems based on accelerometers,the speed phase locked loop(PLL),a kind of high precision speed stability control method,is applied to the electromotor control.
为了提高以加速度计发展起来的非陀螺寻北系统中转台的稳速精度,深入研究了高精度速度稳定控制中的锁相环路控制法在电机稳速控制中的应用,并指出变参数软件锁相环控制是一种获得高精度稳速控制的可行办法。
This unit combined global position system(GPS) with phase locked loop(PLL) technique,and made measured phasor to be sampled synchronously at different site,as well as sampling frequency to follow system frequency variance self-adapt.
该装置将全球定位系统和锁相环技术相结合,既保证了不同测量点被测相量的同步采样,又保证了各测量点对被测相量信号的采样频率能自适应地跟踪电网频率变化,使相量测量精度进一步提高。
A novel all-digital phase locked loop(PLL),applied to the carrier synchronization of communication systems,is designed.
设计了一种用于通信系统载波同步的新数字锁相环。
Behavior Modeling of PLL and Its Application in Video Horizontal PLL
锁相环行为级建模及在视频行锁相中的应用
Single-phase Phase-Locked Loop based on Modified Instantaneous Reactive Power Theory
基于改进瞬时无功理论的单相锁相环
Optimized implementation scheme of three phase phase-locked loop based on FPGA
基于FPGA的三相锁相环的优化设计方案
PLL lock time is below 15us,power dissipation is below 10mw.
该锁相环的锁定时间低于 15us,功耗小于 10mW。
The Study on Performance of Phase-Locked Loop Based on Mode-Locked Fiber Laser;
基于锁模光纤激光器的锁相环特性的研究
Relationship Analysis between PLL Phase Noise and PLL Bandwidth
锁相环相位噪声与环路带宽的关系分析
Analysis of the Magnitude Frequency Responses of Software Phase-Locked Loop and Its Loop Filter
软件锁相环环路滤波器和闭环幅频响应分析
Special PLL used in target RF simulation of the radio detonator
引信目标射频仿真中的特殊锁相环路
A True Random Number Generator Based on PLL
一种基于锁相环的真随机数发生器
A Fast Acquisition PLL with Wide Tuning Range
一种快捕获宽调节范围的锁相环(英文)
Modeling, Design and Implementation of Phase-locked Loop Frequency Synthesizer;
锁相环频率合成器建模、设计与实现
Modeling and Design of Charge Pump Phase-Locked Loops;
电荷泵锁相环的模型研究和电路设计
Design of Fully Integrated Phase-Locked Loop for GPS Receiver;
用于GPS接收机的全集成锁相环设计
Design of Novel Fully-differential Charge Pump for PLL;
锁相环用新型全差分CMOS电荷泵设计
Research and Design of All-digital PLL with High Frequency and Low Jitter Performance;
高速低抖动全数字锁相环的设计研究
Analysis and Design of RF Oscillator and PLL Architecture;
射频振荡器与锁相环结构分析与设计
The Research and Design of CMOS Charge-Pump Phase-Locked Loop;
CMOS电荷泵锁相环的研究与设计
Design of Phase-locked Loop for USB2.0 Application;
应用于USB2.0时钟数据恢复的锁相环设计
