It also introduces how to design a UAT with 16 bytes FIFO.
提供一个用FPGA实现有16字节FIFO的通用异步发送器的设计。
Study and design of an on chip clock generator with high stability;
一种高稳定度片内时钟发生器的研究与设计
Principle and application of high performance programmable line-locked clock generator ICS1523;
ICS1523型高性能可编程行同步时钟发生器的原理及应用
Circuit design of spread-spectrum clock generator based on DP standard
基于DP标准发射端扩频时钟发生器电路设计
boosted-high level clock generator
升压高电平时钟发生器
DRCG Direct Rambus clock generator
直接RAMBUS时钟发生器
Design and Analysis of CMOS PLL Clock Generator;
CMOS锁相环时钟发生器的设计与研究
Design and Implementation of Wideband High-Performance TIADC Clock Generator
一种宽带高性能TIADC时钟发生器
Scheme of Fast Self-Calibration for a FPGA Chip Clock Generator
FPGA片上时钟发生器快速自校准方案
Circuit design of spread-spectrum clock generator based on DP standard
基于DP标准发射端扩频时钟发生器电路设计
Design of a Spread‐Spectrum Clock Generator for DisplayPort Standard;
一种用于DisplayPort标准的扩频时钟发生器设计
Research of spread-spectrum clock generator system parameters based on DP standard
基于DP标准的扩频时钟发生器系统参数研究
The ADC aperture jitter must be minimal, and the sampling clock generated from a low phase-noise quartz crystal oscillator.
ADC的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。
TV station clock mark generator
电视台时钟台标发生器
single-phase clock generator
单相时钟脉冲发生器
clock pulse generator
时钟脉冲发生器同步脉冲发生器
Represents a crystal clock signal generator. Number of electrodes can be specified.
表示晶体时钟信号发生器。可指定电极数目。
A Clock Generation Circuit for High-Resolution ∑Δ Modulator;
适用于高精度Δ调制器的低电压时钟发生电路
MADL Based Cycle Accurated Simulator Generation;
基于MADL语言的时钟精确级仿真器生成
horological industry
钟表[计时器]工业
The sampling clock generator must also have adequate spectral purity.
时钟发生电路固有的抖动应该足够小。
Design of Clock Generation and Drive Circuits in High Speed CIS System
高速CIS时钟发生电路及驱动电路设计
