A multi-mode FPGA logic cell and a technology mapping tool VMAP are presented.
结合FPGA设计的特点,提出一种可灵活配置的多模式FPGA逻辑单元结构及对其进行工艺映射的工具VMAP。
This paper provides a novel FPGA logic cell based on improvement carry chains,which is verified with 4×4 binary multipliers.
提出了一种基于改进进位链的FPGA逻辑单元结构,并用4×4二进制乘法器进行了验证。
There is a I/O interface and logical blocks CLB in it.
内部具有独立的 I/O接口和逻辑单元 CL B。
The arithmetic logic unit (ALU), which performs arithmetic and logical operations.
算术逻辑单元，用来进行算术逻辑运算。
Light Controlled MOBILE with the RTD/HPT Structure
RTD/HPT光控单-双稳转换逻辑单元
To prevent a device or logic element from producing a specified output.
防止一个设备或逻辑单元产生某一特定的输出。
CORRELATIVE DESIGNS AND DISCUSSIONS OF AN ALU IN A DATA PATH
数据通路中算术逻辑单元相关设计与探讨
Technology Mapping for FPGA with Multi-mode Logic Cell
针对一种多模式逻辑单元结构FPGA的工艺映射
An asynchronous GALS wrapper based on standard logic cell
一种基于标准逻辑单元的GALS异步封装电路
Standard logic cells, memory design and IO Layout design.
标准逻辑单元,存储电路设计及输入输出单元版图设计。
In SNA products, a request to activate a session between two logical units.
在系统网络体系结构（SNA）产品中，激活两个逻辑单元间的话路的请求。
The stomach and duodenum may be considered logically as a unit.
胃和十二指肠可逻辑地考虑为一个单元。
Research of the Distributed Logic Control and Detecting Unit in Electric Locomotive;
电力机车分布式逻辑控制与检测单元的研究
Josephson tunnel logic
约瑟夫逊隧道逻辑元件
static logic diode element
静态逻辑二极管元件
static logic transistor element
静态逻辑晶体管元件
BILE (Balanced Inductor Logical Element)
平衡式感应器逻辑元件
logical algebraic equatin with two unknowns
二元逻辑代数方程式
balanced inductor logical element
平衡式感应逻辑元件
(math or logic) not monotonic.
（数学或逻辑）不单调的。
single-ended pair logic circuit
单端输出偶逻辑电路
