In order to reduce the power dissipation correlative with redundant states in sequential circuits and the redundant leap of the lock, low power design of decimal counter is proposed in this paper.
本文从抑制时序电路中的冗余状态、时钟信号冗余跳变产生的额外功耗出发,提出了一种低功耗十进制计数器的新设计。
Based on the working principle,counter structure and Clocked Transmission Gate Adiabatic Logic circuits,a design scheme of decimal counter with reset is proposed.
通过对计数器和钟控传输门绝热逻辑电路工作原理及结构的研究,提出一种带复位功能的低功耗十进制计数器设计方案。
binary-decade counter
二进制——十进制计数器
binary-coded decimal counter
二-十进制编码计数器
BCD decode counter
二-十进制译码计数器
Design of Low-power Decimal Counter with Reset Based on CTGAL Circuit
基于CTGAL电路的低功耗十进制复位计数器设计
multiple-digit decimal adder
多数位的十进制加法器
biquinary scaler
二五混合进制计数器
single core binary counter
单磁心二进制计数器
binary contact making counter
二进制接触式计数器
The design progress of this sequence generator starts with the listing of sequence both in decimal and binary.
在进行序列产生器的设计时，首先用十进制数和二进数同时列出所需要的序列。
DDDA (Decimal Digital Differential Analyzer)
十进制位的数字微分方程解算器
binary gas mixture scaler
二进制换算电路二进制计数器
Normally, a four bit binary counter would increment up to1111(decimal15) before returning to0.
通常，一个四位二进制计数器在返回到0之前可增加到1111（即十进制的15）。
decimal to binary encoder
十进制与二进制编码器
METHOD FOR ANY NUMBER BY INTEGRATION COUNTER;
集成计数器构成任意进制计数器的方法
We are used to writing numbers in base ten, using 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
我们习惯使用0，1，2，3，4，5，6，7，8，9的十进制计数方法。
The fixed radix numeration system that uses the decimal digits and the radix 10 and in which the lowest integral weight is 1.
采用十进制数字和基数为十的固定基数的计数制。在这种计数制中最小整数权是1。
decimal computer
十进位（制）计算机
Design of module-N synchronous counter based on MSI;
基于MSI的任意进制计数器的设计
