Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed.
提出了两种新的电路技术,在降低多输入多米诺“或门”的动态功耗的同时减小了漏电流,并提高了电路的噪声容限。
Some problems such as static-noise margin(SNM) caused by reducing bitline voltage are also discussed in this paper.
同时本文还分析了由于位线电压降低带来的静态噪声容限(SNM)等问题。
The analytical Static Noise Margin (SNM) model for Very Deep Submicron (VDSM) SRAM memory cell is developed, which is based on physical α power MOSFET model.
采用基于物理模型的 α指数 MOSFET模型 ,对超深亚微米 (VDSM:Very Deep Submicron) SRAM存储单元的静态噪声容限 (SNM:Static Noise Margin)进行了解析分析 ,分析中考虑了随机工艺涨落造成的VDSM SRAM存储单元阈值失配对 SNM的影响 ,结果与 HSPICE仿真相符 ;文中同时分析了栅宽与 SNM的关系 ,其结论与实验结果一致 ,并给出了 VDSM SRAM存储单元设计中应注意的问
The basic principles, advantages, disadvantages and an important parameter named SNM (static noise margin) of a SRAM (static random access memory) 6 Transistor (6T) storage cell were analyzed and summarized firstly.
文章首先分析了静态随机存储器(SRAM)6T存储单元结构的基本工作原理,总结了6T存储单元的优缺点并介绍了存储单元的重要参数静态噪声容限(SNM)。
